Q21GATE 2005MCQ

Select the circuit, which will produce the given output Q for the input signals $X_{1}$ and $X_{2}$ given in the figure

📖 Explanation

\begin{matrix} S & R & \\ X_1 & X_2 & Q^+\\ 1 & 0 & 1\\ 0 & 0 & NC\\ 0 & 1 &0 \\ 1 &0 &1 \\ 0 & 1 & 0\\ 1& 0 & 1 \end{matrix}

From the above table we can write,

\begin{matrix} S & R & Q^+\\ 0 & 0 & NC\\ 0 & 1 &0 \\ 1 &0 &1 \\ 1 & 1 & X \end{matrix}

Q23GATE 2004MCQ

The digital circuit shown in figure generates a modified clock pulse at the output. Choose the correct output waveform from the options given below.

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Q24GATE 2004MCQ

The digital circuit using two inverters shown in figure will act as

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Q25GATE 2003MCQ

The shift register shown in figure is initially loaded with the bit pattern 1010. Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position (msb). After how many clock pulses will the content of the shift register become 1010 again ?

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Q26GATE 2003MCQ

An X-Y flip-flop, whose Characteristic Table is given below is to be implemented using a J-K flip flop

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📖 Explanation

To make (X-Y) FF using (J-K) FF, (J) should be $(\bar{Y})$ and (K) should be (X).

Q27GATE 2002MCQ

The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 kHz. The frequency of the signal available at Q is

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📖 Explanation

In toggle mode $f_{out}=\frac{f_{\in}}{2}=\frac{10kHz}{2}=5kHz$