Sequential Logic Circuits Practice Questions

Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with clock, is

The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flipflops, with each flip-flop having a propagation delay of 20 ns, is ___________. (round off to one decimal place)

A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)

A 16-bit synchronous binary up-counter is clocked with a frequency $f_{\text{CLK}}$ .The two most significant bits are $\text{OR-ed}$ together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is $\text{24 ms}$ . The clock frequency $f_{\text{CLK}}$ is ___________ $\text{MHz}$ . (Round off to 2 decimal places.)

A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0): what is the output of this detector?

Which one of the following statements is true about the digital circuit shown in the figure

For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions $Q_{A}Q_{B}Q_{C}=Q_{A}'Q_{B}'Q'_{C}=100$ The minimum number of clock cycles after which the output Z would again become zero is ________

The current state $Q_{A}Q_{B}$ of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is

In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is $Q_{1}Q_{0}$ =00. The state ( $Q_{1}Q_{0}$ ), immediately after the $333^{rd}$ clock pulse is

The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of $Q_{2}Q_{1}Q_{0}=000$ . This state $Q_{2}Q_{1}Q_{0}=000$ will repeat after _______ number of cycles of the clock CLK

A JK flip flop can be implemented by T flip-flops. Identify the correct implementation.

A cascade of three identical modulo-5 counters has an overall modulus of

A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don't care condition, and Q is the output representing the state. The logic gate represented by the state diagram is

The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is '0', then the frequency of the output waveform Q in kHz is

Consider the given circuit In this circuit, the race around

The state transition diagram for the logic circuit shown is

A two bit counter circuit is shown below If the state $Q_A Q_B$ of the counter at the clock time $t_n$ is '10' then the state $Q_AQ_B$ of the counter at $t_n+3$ (after three clock cycles) will be

The digital circuit shown in the figure works as

In the figure, as long as $X_{1}$ = 1 and $X_{2}$ = 1, the output Q remains