Assume that the N-channel MOSFET shown in the figure is ideal, and that its threshold voltage is +1.0 V. The voltage between nodes a and b is:

GATE EE · Analog Electronics
Generate GATE-level questions on Transistor Biasing. Focus on: 1. BJT and FET (JFET/MOSFET) characteristics and regions of operation. 2. Biasing techniques: Fixed bias, Voltage divider bias, and Collector-to-base bias. 3. Stability factor and Thermal runaway basics.
30 questions · 10 PYQs · 0 AI practice · GATE EE 2027
Assume that the N-channel MOSFET shown in the figure is ideal, and that its threshold voltage is +1.0 V. The voltage between nodes a and b is:

Assume that the threshold voltage of the N-channel MOSFET shown in figure is + 0.75 V. The output characteristics of the MOSFET are also shown The voltage gain of the amplifier is

Two perfectly matched silicon transistor are connected as shown in figure. The value of the current I is
The transconductance of the transistor shown in figure is 10 mS. The value of the input resistance is

The value of R for which the PMOS transistor in figure will be biased in linear region is

In the circuit of figure, assume that the transistor has = 99 and = 0.7 V. The value of collector current of the transistor is approximately

For the n-channel enhancement MOSFET shown in figure, the threshold voltage = 2 V. The drain current of the MOSFET is 4 mA when the drain resistance is 1 k . If the value of is increased to 4 k , drain current will become

The variation of drain current with gate-to-source voltage ( - characteristic) of a MOSFET is shown in figure. The MOSFET is

In the circuit shown in figure, the current gain ( ) of the ideal transistor is 10. The operating point of the transistor ( ) is

An n-channel JFET, having a pinch-off voltage ( ) of -5 V, shows a transconductance ( ) of 1 mA/V when the applied gate-to-source voltage ( ) is -3V. Its maximum transconductance (in mA/V) is
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