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GATE EE · Analog Electronics

Bjt Fet And Their Biasing Circuits Practice Questions

Generate GATE-level questions on Transistor Biasing. Focus on: 1. BJT and FET (JFET/MOSFET) characteristics and regions of operation. 2. Biasing techniques: Fixed bias, Voltage divider bias, and Collector-to-base bias. 3. Stability factor and Thermal runaway basics.

30 questions · 20 PYQs · 0 AI practice · GATE EE 2027

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Q1GATE 2024MCQ

A BJT biasing circuit is shown in the figure, where $V_{B E}=0.7 \mathrm{~V}$ and $\beta=100$ . The Quiescent Point values of $V_{C E}$ and $I_{C}$ are respectively

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📖 Explanation

\begin{aligned} & V_{\text {Th }}=\frac{12 \times 50 k}{150 k}=4 \mathrm{~V} \\ & R_{\text {Th }}=50 \mathrm{k} \| 100 \mathrm{k}=\frac{50 \mathrm{k} \times 100 \mathrm{k}}{150 \mathrm{k}}=33.33 \mathrm{k} \Omega \end{aligned}

$\mathrm{KVL}$ in input loop, $4-33.33 k \times I_{B}-0.7-I_{E} R_{E}=0$ $3.3-33.33 k \times I_{B}-(1+\beta) I_{B} \times 1 k=0$ $\therefore \quad I_{B}=\frac{3.3}{33.33 \mathrm{k}+101 \mathrm{k}}=24.56 \mu \mathrm{A}$ $I_{C}=\beta I_{B}=100 \times 24.56 \times 10^{-6}=2.46 \mathrm{~mA}$ $I_{E}=(1+\beta) I_{B}=2.47 \mathrm{~mA}$ $\mathrm{KVL}$ in outer loop :

\begin{aligned} 12-2 k \times I_{C}- & V_{C E}-I_{E} R_{E}=0 \\ & 12-V_{C E}=2 \mathrm{k} \times I_{C}+I_{E} \times 1 \mathrm{k} \\ & 12-V_{C E}=7.39 \Rightarrow V_{C E}=4.61 \mathrm{~V} \end{aligned}

Explanation Figure 2

Q2GATE 2023MSQ

All the elements in the circuit shown in the following figure are ideal. Which of the following statements is/are true?

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📖 Explanation

Case (i): Switch $\mathrm{S}$ is ON Assume $\mathrm{D}_{3} \rightarrow$ OFF, $D_{2} \rightarrow$ OFF and $\mathrm{D}_{1} \rightarrow \mathrm{ON}$ Redraw the circuit : $\therefore$ Our assumption is correct. Case (ii) : Switch $\mathrm{S}$ is OFF. Then, $\mathrm{D}_{3} \rightarrow \mathrm{ON}, \mathrm{D}_{2} \rightarrow \mathrm{ON}$ and $\mathrm{D}_{1} \rightarrow \mathrm{OFF}$ Redraw the circuit : $\therefore$ Circuit satisfy this condition also. Hence, option (B) and (C) will be correct.

Explanation Figure 2

Explanation Figure 3

Q3GATE 2021NAT

In the $\text{BJT}$ circuit shown, beta of the $\text{PNP}$ transistor is 100. Assume $V_{\text{BE}}=-0.7\;V$ . The voltage across $R_{c}$ will be $\text{5 V}$ when $R_{2}$ is __________ $k \Omega$ . (Round off to 2 decimal places.)

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📖 Explanation

\begin{aligned} I_{C}&=\frac{5 \mathrm{~V}}{3.3 \mathrm{k}}=1.515 \mathrm{~mA} \\ I_{E}&=1.53 \mathrm{~mA} \\ I_{B}&=0.0151 \mathrm{~mA}\\ -12+1.2 \mathrm{k} \times 1.53 \mathrm{~m}+& 0.7+V_{B}=0 \\ V_{B} &=9.464 \mathrm{~V} \\ I_{x} &=\frac{12-V_{B}}{4.7 \mathrm{k}}=\frac{12-9.464}{4.7 \mathrm{k}}=0.539 \mathrm{~mA} \\ I_{x}+I_{B} &=I_{y} \\ \Rightarrow \qquad\qquad I_{y} &=0.5396+0.0151 \\ I_{y} &=0.5546 \mathrm{~mA} \\ V_{B} &=0.5546 \mathrm{~m} \times R_{2}=9.464 \\ R_{2} &=17.06 \mathrm{k} \Omega \end{aligned}

Explanation Figure 2

Q4GATE 2020NAT

The cross-section of a metal-oxide-semiconductor structure is shown schematically. Starting from an uncharged condition, a bias of +3V is applied to the gate contact with respect to the body contact. The charge inside the silicon dioxide layer is then measured to be +Q. The total charge contained within the dashed box shown, upon application of bias, expressed as a multiple of Q (absolute value in Coulombs, rounded off to the nearest integer) is __________ .

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📖 Explanation

Overall charge in side the box $q + q - q - q = 0$ charge

Explanation Figure 2

Q5GATE 2019MCQ

Given, $V_{gs}$ is the gate-source voltage, $V_{ds}$ is the drain source voltage, and $V_{th}$ is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are

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📖 Explanation

For NMOS transistor to be in saturation the condition will be $V_{gs} \gt V_{th}$ and $V_{ds} \geq V_{gs}-V_{th}$

Q6GATE 2019MCQ

The enhancement type MOSFET in the circuit below operates according to the square law. $\mu_nC_{ox}=100\mu A/V^2$ , the threshold voltage ( $V_T$ ) is 500 mV. Ignore channel length modulation. The output voltage $V_{out}$ is

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📖 Explanation

As, $V_{DS}=V_{GS}$ MOSFET is in saturation,

\begin{aligned} I_D&=\frac{1}{2}\mu _nC_{Ox}\left ( \frac{W}{L} \right )(V_{GS}-V_T)^2 \\ 5 \times 10^{-6}&=\frac{1}{2} \times 100 \times 10^{-6} \times 10 (V_{GS}-0.5)^2\\ V_{GS}&=0.6 \\ V_0&=600mV \end{aligned}

Explanation Figure 2

Q7GATE 2018NAT

In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain $\beta=100$ . The base-emitter voltage drop is a constant, $V_{BE}= 0.7$ V. The value of the The venin equivalent resistance $R_{Th}$ (in $\Omega$ ) as shown in the figure is ______ (up to 2 decimal places).

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📖 Explanation

To calculate $R_{Th}$ D.C. volatage should be short circuited. $R_{Th}=1k\Omega ||\frac{10k}{1+\beta }$ $\; \; =1k\Omega ||99.0099$ $R_{Th}=90.09\Omega$

Explanation Figure 2

Explanation Figure 3

Q8GATE 2017NAT

The circuit shown in the figure uses matched transistors with a thermal voltage $V_T$ =25mV. The base currents of the transistors are negligible. The value of the resistance R in k $\Omega$ that is required to provide 1 $\mu$ A bias current for the differential amplifier block shown is ______.

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📖 Explanation

$V_{BE1}=V_{BE2}+I_0R$ $I_0R=V_{BE1}-V_{BE2} =V_I ln\left ( \frac{I_R}{I_3} \right )-V_T ln \left ( \frac{I_0}{I_3} \right )$ where, $I_s\rightarrow$ Reverse saturation current $R=\frac{V_T ln\left ( \frac{I_R}{I_0} \right )}{I_0}=\frac{0.025 ln\left ( \frac{1mA}{1\mu A} \right )}{1\mu A} =\frac{0.025 ln (10^3)}{1\mu A}=172.7 k\Omega$

Explanation Figure 2

Q9GATE 2017MCQ

For the circuit shown in the figure below, it is given that $V_{CE}=\frac{V_{CC}}{2}$ . The transistor has $\beta =29$ and $V_{BE}=0.7V$ when the B-E junction is forward biased. For this circuit, the value of $\frac{R_B}{R}$ is

🚀 Solve in Practice Mode

📖 Explanation

In the input loop, $10=(1+\beta )I_B \times 4R+I_B \times R_B+0.7+(1+\beta )I_B \times R$ $10=30I_B \times 4R+I_B \times R_B+0.7+30 \times I_B \times R$ $9.3=150 \times I_B \times R +I_B \times R_B .....(i)$ Ouput loop, $10=(1+\beta )I_B \times 4R+5V+(1+\beta )I_B \times R$ $5=30I_B \times 4R+30 \times I_B \times R$ $5=150 \times I_B \times R .....(ii)$ using equation (i) and (ii), $I_BR_B=9.3-5=4.3$ and simultaneously putting value of $I_B R$ from equation (ii) in equation (i), $9.3=I_BR\left[ 150+\frac{R_B}{R} \right]$ $9.3=\frac{5}{150}\left[ 150+\frac{R_B}{R} \right]$ $279=150+\frac{R_B}{R}$ $\frac{R_B}{R}=129$

Q10GATE 2016NAT

A transistor circuit is given below. The Zener diode breakdown voltage is 5.3 V as shown. Take base to emitter voltage drop to be 0.6 V. The value of the current gain $\beta$ is _________.

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📖 Explanation

$V_B=5.3 V$ $V_E=V_B-0.6=4.7V$ $I_E=\frac{V_E}{470\Omega }=10mA$ $I_1=\frac{10-5.3}{4.7k}=1mA$ $I_B=I_1-I_2=0.5mA$ $\frac{I_E}{I_B}=\beta +1=20$ $\beta =19$

Explanation Figure 2

Q11GATE 2015NAT

In the given circuit, the silicon transistor has $\beta$ =75 and a collector voltage $V_c$ =9 V. Then the ratio of $R_{B}$ and $R_{C}$ is ________.

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📖 Explanation

Consider the circuit shown in figure. $V_C=9V$ $So,\;\; \frac{15-9}{R_C}=I_E$ $\frac{6}{R_C}=I_E$ $and \;\;\frac{9-0.7}{R_B}=I_B$ $So,\;\;\frac{8.3}{R_B}=I_B$ $So, \;\; \frac{I_E}{I_B}=\frac{6 \times R_B}{R_C \times 8.3}$ $(\beta +1)=\frac{R_B \times 6}{R_C \times 8.3}$ $\frac{R_B}{R_C}=105.13$

Explanation Figure 2

Q12GATE 2015NAT

In the following circuit, the transistor is in active mode and $V_{C}$ =2 V. To get $V_{C}$ =4 V, we replace $R_{C}$ with $R^{'}_{C}$ . Then the ratio $R^{'}_{C}/R_{C}$ is ______.

🚀 Solve in Practice Mode

📖 Explanation

CASE-I: $V_C=2V$ $i_C=\frac{10-2}{R_C} ......(i)$ $10-i_BR_B-0.7=0$ $i_B=\frac{10-0.7}{R_B} .......(ii)$ CASE-II when $V_C=4V$ $R_C\rightarrow R'_C$ $i_C=\frac{10-4}{R'_C} .....(iii)$ From above equation (iii) and (i), $\frac{10-4}{R'_C}= \frac{10-2}{R_C}$ $\Rightarrow \frac{R'_C}{R_C}=\frac{6}{8}=\frac{3}{4}=0.75$

Explanation Figure 2

Q13GATE 2015MCQ

When a bipolar junction transistor is operating in the saturation mode, which one of the following statements is TRUE about the state of its collector-base (CB) and the base-emitter (BE) junctions?

🚀 Solve in Practice Mode

📖 Explanation

Currently no explanation available

Q14GATE 2014NAT

The transistor in the given circuit should always be in active region. Take $V_{CE(sat)}=0.2V,\; V_{BE}=0.7V$ . The maximum value of $R_c \; \in \; \Omega$ which can be used, is _____.

🚀 Solve in Practice Mode

📖 Explanation

In input loop: $I_b=\frac{5-0.7}{2k\Omega }=\frac{4.3}{2k\Omega }=2.15 mA$ $So, \; \; I_c=\beta \times I_b=100 \times 2.15mA$ $=0.215 A$ Now KVL in output loop: $V_{CE}=5-0.215R_C$ For active region $V_{CE} \gt 0.2V$ $\Rightarrow 0.215R_C \lt 5-0.2$ $\Rightarrow R_{Cmax}=\frac{4.8}{0.215}\simeq 22.32\Omega$

Q15GATE 2012MCQ

The voltage gain $A_v$ of the circuit shown below is

🚀 Solve in Practice Mode

📖 Explanation

Equivalent A.C. model will be taking, $h_{ie}=1k\Omega$ $h_{fe}=\beta =100$ $A_V=\frac{V_o}{V_{\in}}=\frac{-h_{fe}i_b \times (100||12)k\Omega }{h_{ie}\times i_b}$ $A_V=\frac{-100 \times 10.71k\Omega }{1k\Omega }=-1071.42$ $V_i=h_{ie}i_b+10^4i$ $V_i=10^3i_b+10^4\left[ i_b+\frac{h_{ie}\times i_b}{\left ( \frac{100k\Omega }{1-A_V} \right )} \right]$ $V_i=10^3i_b+i_b[10^{4+}(1071.42)\times 100]$ $A_{VS}=\frac{V_o}{V_i}=\frac{-h_{fe}i_b \times 10.7142 \times 10^3}{i_b\$ [10^{3+}10^{4+}10^2× 1071.42]$}A_{VS}=\frac{-100 \times 10.7142 \times 10^3}{(10^{3+}10^{4+}10^2\times 1071.42)}A_{VS}=-9.06 |A_{VS}|=9.06\approx 10$

Explanation Figure 2

Explanation Figure 3

Q16GATE 2010MCQ

The transistor circuit shown uses a silicon transistor with $V_{BE}=0.7 V, I_C\approx I_E$ and a dc current gain of 100. The value of $V_{0}$ is

🚀 Solve in Practice Mode

📖 Explanation

$KVL\Rightarrow$ $\; \; \; 10=10kI_b+0.7+(100)(I_b)100$ $\; \; \; I_b=\frac{9.3}{20k}=0.465 mA$ $\; \; \; V_o=100\times 0.465\times 100=4.65 V$

Q17GATE 2008MCQ

Two perfectly matched silicon transistor are connected as shown in the figure assuming the $\beta$ of the transistors to be very high and the forward voltage drop in diodes to be 0.7 V, the value of current I is

🚀 Solve in Practice Mode

📖 Explanation

Since both transitor are perfectly matched, So, $V_{BE1}=V_{BE2}$ $\frac{I_{c1}}{I_{c2}}=exp\left[ \frac{V_{BE1}-V_{BE2}}{V_T} \right]=e^0=1$ Since \beta for both are same, therefore $I_{b1}=I_{b2}=I_{b}$ Applying KVL to loop as shown, $I_R=\frac{0-0.7-0.7-(-5)}{1k\Omega }=3.6mA$ By KCL, $I_R=I_c+2I_b$ $\;\; =I_c+2\frac{I-c}{\beta }$ $\therefore \; I_c=\frac{\beta }{\beta +2}\times I_R$ $\;\; \approx I_R$ (Because $\beta$ is very large)

Explanation Figure 2

Q18GATE 2007MCQ

The common emitter forward current gain of the transistor shown is $\beta _{F}=100$ . The transistor is operating in

🚀 Solve in Practice Mode

📖 Explanation

We assume BJT is in active region, applying KVL in base emitter circuit $10-0.7=1k\Omega \times I_c+270 \times I_b$ $=I_b(270+100k)$ $\therefore \; \; I_b=\frac{9.3}{370}mA$ $\therefore \;\; I_c=\frac{93}{37}mA$ $I_{c(sat)}=\frac{10-0.2}{2k}=4.9 mA$ $I_{c(sat)} \gt I_{c(active)}$ $\therefore \;$ BJT is in active region.

Q19GATE 2006MCQ

Consider the circuit shown in figure. If the $\beta$ of the transistor is 30 and $I_{CBO}$ is 20 mA and the input voltage is +5 V, the transistor would be operating in

🚀 Solve in Practice Mode

📖 Explanation

Assume BJT is in active Region and we neglect $I_{CBO}$ ,

\begin{aligned} V_{th}&=\frac{-12 \times 15}{115}+\frac{5 \times 100}{5} \\ &=2.78 V \\ R_{th}&=(15||100)\\ &=\frac{15 \times 100}{5}=13 k\Omega \\ I_c&=\beta I_b \\ \text{But, } I_b&=\frac{2.78-0.7}{13}=0.16mA \\ I_c&=4.8 mA \\ \text{But, }I_{c(sat)}&=\frac{12-0.2}{2.2k}=5.36mA \\ \text{as } I_{c(sat)} & \gt I_{c(active)}\end{aligned}

BJT is in active region.

Explanation Figure 2

Q20GATE 2005MCQ

The common emitter amplifier shown in the figure is biased using a 1 mA ideal current source. The approximate base current value is

🚀 Solve in Practice Mode

📖 Explanation

$\beta =\frac{I_c}{I_b}$ $I_b=\frac{1 \times 10^{-3}}{100}=10 \mu A$

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