Q2GATE 2013MCQ

In the circuit shown below, $Q_{1}$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}$ is +5 V, X and Y are digital signals with 0 V as logic 0 and $V_{cc}$ as logic 1, then the Boolean expression for Z is

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📖 Explanation

$\Rightarrow \;\;Z=\bar{X}Y$

Q3GATE 2010MCQ

The TTL circuit shown in the figure is fed with the waveform X (also shown). All gates have equal propagation delay of 10 ns. The output Y of the circuit is

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Q4GATE 2006MCQ

A TTL NOT gate circuit is shown in figure. Assuming $V_{BE}$ =0.7 V of both the transistors, if $V_{i}$ =3.0 V, then the states of the two transistors will be

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📖 Explanation

When $V_i=3 V$ then $Q_1$ will be in reverse active mode i.e. reverse ON and $Q_2$ will be ON.

Q5GATE 2005MCQ

If $X_{1}$ and $X_{2}$ are the inputs to the circuit shown in the figure, the output Q is

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📖 Explanation

$Y_1=\bar{X_1}$ Output, $Q=\overline{Y_1+X_2}=\overline{(\bar{X_1}+X_2)}$ $Q=X_1\cdot \bar{X_2}$

Logic Families And Miscellaneous Practice Questions

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