GATE EE · Digital Electronics
Generate GATE-level questions on Data Converters. Focus on: 1. Digital-to-Analog Converters (DAC): R-2R ladder and Weighted resistor types. 2. Analog-to-Digital Converters (ADC): Flash, Successive Approximation (SAR), and Dual-slope. 3. Resolution, Quantization error, and Conversion time calculations.
10 questions · 10 PYQs · 0 AI practice · GATE EE 2027
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An 8-bit ADC converts analog voltage in the range of 0 to to the corresponding digital code as per the conversion characteristics shown in figure. For , which of the following digital output, given in hex is true?

A 2-bit flash Analog to Digital Converter (ADC) is given below. The input is Volts. The expression for the LSB of the output as a Boolean function of is

A temperature in the range of -40 C to 55 C is to be measured with a resolution of 0.1 C. The minimum number of ADC bits required to get a matching dynamic range of the temperature sensor is
An 8-bit, unipolar Successive Approximation Register type ADC is used to convert 3.5 V to digital equivalent output. The reference voltage is +5 V. The output of the ADC, at the end of 3rd clock pulse after the start of conversion, is
The Octal equivalent of HEX and number AB.CD is
It is required to design an anti-aliasing filter for an, 8 bit ADC. The filter is a first order RC filter with R = 1 and C = 1F. The ADC is designed to span a sinusoidal signal with peak to peak amplitude equal to the full scale range of the ADC. What is the SNR (in dB) of the ADC ? Also find the frequency (in decades) at the filter output at which the filter attenuation just exceeds the SNR of the ADC.

A student has made a 3-bit binary down counter and connected to the R-2R ladder type DAC [Gain=(-1K /2R)] as shown in figure to generate a staircase waveform. The output achieved is different as shown in figure. What could be the possible cause of this error ?

The voltage comparator shown in figure can be used in the analog-to-digital conversion as

Among the following four, the slowest ADC (analog-to-digital converter) is
A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at the input of an ADC (analog-to-digital converter). The conversion time of the ADC is 1 sec, and during this time, the capacitor should not lose more than 0.5% of the charge put across it during the sampling time. The maximum value of the input signal to the S/H circuit is 5V. The leakage current of the S/H circuit should be less than
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