Q21GATE 2005MCQ

Both transistors $T_{1}$ and $T_{2}$ show in the figure, have a threshold voltage of 1 Volts. The device parameters $K_{1}$ and $K_{2}$ of $T_{1}$ and $T_{2}$ are, respectively, 36 $\mu A/V^{2}$ and 9 $\mu A/V^{2}$ . The output voltage Vo is

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📖 Explanation

\begin{aligned} I_{D_{1}} &=I_{D_{2}} \\ K_{1}\left(V_{G S 1}-V_{t}\right)^{2} &=K_{2}\left(V_{G S_{2}}-V_{t}\right)^{2} \\ \Rightarrow 36\left(5-V_{0}-1\right)^{2} &=9\left(V_{0}-0-1\right)^{2} \\ \Rightarrow \quad V_{0} &=3 \mathrm{V} \end{aligned}

Q22GATE 2004MCQ

The figure the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in the figure, the output Y is

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📖 Explanation

For TTL logic floating input =1 $\therefore \quad Y=(A B+1)^{\prime}=\overline{A B} \cdot 0=0$

Q23GATE 2004MCQ

Given figure is the voltage transfer characteristic of

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Q24GATE 2003MCQ

The output of the 74 series of GATE of TTL gates is taken from a BJT in

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Q25GATE 2003MCQ

The DTL, TTL, ECL and CMOS famil GATE of digital ICs are compared in the following 4 columns The correct column is

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Q26GATE 2002MCQ

The circuit in figure has two CMOS NOR gates. This circuit functions as a:

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Q27GATE 2001MCQ

In the TTL circuit in figure, $S_{2}$ to $S_{0}$ are select lines and $X_{7}$ and $X_{0}$ are input lines. $S_{0}$ and $X_{0}$ are LSBs. The output Y is

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📖 Explanation

Floating input is accepted by TTL logic gate as logic 1 Hence $S_{2} = 1$ $Y=A \oplus B$