Fet And Mosfet Analysis Practice Questions

Which of the following statements is/are TRUE with respect to ideal MOSFET-based DC-coupled single-stage amplifiers having finite load resistors?

In the circuit below, assume that the long channel NMOS transistor is biased in saturation. The small signal trans-conductance of the transistor is $g_{m}$ Neglect body effect, channel length modulation and intrinsic device capacitances. The small signal input impedance $Z_{\text {\in }}(j \omega)$ is _____

In the circuit shown below, the transistors $M_{1}$ and $M_{2}$ are biased in saturation. Their small signal transconductances are $g_{m 1}$ and $g_{m 2}$ respectively. Neglect body effect, channel length modulation and intrinsic device capacitances. Assuming that capacitor $C_{1}$ is a short circuit for $A C$ analysis, the exact magnitude of small signal voltage gain $\left|\frac{v_{\text {out }}}{v_{\text {\in }}}\right|$ is _______

In the circuit below, the voltage $V_{L}$ is ____ $\_V$ . (rounded off to two decimal places)

For a MOS capacitor, $V_{f b}$ and $V_{t}$ are the flat-band voltage and the threshold voltage, respectively. The variation of the depletion width $\left(W_{\text {dep }}\right)$ for varying gate voltage $\left(V_{g}\right)$ is best represented by

Consider the circuit shown with an ideal long channel nMOSFET (enhancementmode, substrate is connected to the source). The transistor is appropriately biased in the saturation region with $V_{GG}$ and $V_{DD}$ such that it acts as a linear amplifier. $v_i$ is the small-signal ac input voltage. $v_A$ and $v_B$ represent the small-signal voltages at the nodes A and B, respectively. The value of $\frac{v_A}{v_B}$ is ________ (rounded off to one decimal place).

Consider an ideal long channel nMOSFET (enhancement-mode) with gate length $10\mu m$ and width $100\mu m$ . The product of electron mobility ( $\mu _n$ ) and oxide capacitance per unit area ( $C_{OX}$ ) is $\mu _n C_{OX}=1mA/V^2$ . The threshold voltage of the transistor is 1 V. For a gate-to-source voltage $V_{GS}=[2-\sin (2t)]V$ and drain-tosource voltage $V_{DS}=1V$ (substrate connected to the source), the maximum value of the drain-to-source current is ________.

The ideal long channel nMOSFET and pMOSFET devices shown in the circuits have threshold voltages of 1 V and -1 V, respectively. The MOSFET substrates are connected to their respective sources. Ignore leakage currents and assume that the capacitors are initially discharged. For the applied voltages as shown, the steady state voltages are ______

Consider the CMOS circuit shown in the figure (substrates are connected to their respective sources). The gate width ( $W$ ) to gate length ( $L$ ) ratios $\frac{W}{L}$ of the transistors are as shown. Both the transistors have the same gate oxide capacitance per unit area. For the pMOSFET, the threshold voltage is -1 V and the mobility of holes is $40\frac{cm^2}{V.s}$ . For the nMOSFET, the threshold voltage is 1 V and the mobility of electrons is $300\frac{cm^2}{V.s}$ . The steady state output voltage $V_o$ is ________.

Using the incremental low frequency small-signal model of the MOS device, the Norton equivalent resistance of the following circuit is

An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to -10 V. If the input voltage $V_I$ lies between $\pm 10$ V, the minimum and the maximum values of $V_G$ required for proper sampling and holding respectively, are

In the circuit shown, the threshold voltages of the pMOS (| $V_{tp}$ |) and nMOS ( $V_{tn}$ ) transistors are both equal to 1 V. All the transistors have the same output resistance $r_{ds}$ of 6 M $\Omega$ . The other parameters are listed below: $\mu_n C_{ox}=60\mu A/V^2$ ; $\left ( \frac{W}{L} \right )_{nMOS}=5$ $\mu_p C_{ox}=30\mu A/V^2$ ; $\left ( \frac{W}{L} \right )_{pMOS}=10$ $\mu_n \; and \; \mu_p$ are the carrier mobilities, and $C_{ox}$ is the oxide capacitance per unit area. Ignoring the effect of channel length modulation and body bias, the gain of the circuit is____ (rounded off to 1 decimal place).

A CMOS inverter, designed to have a mid-point voltage $V_I$ equal to half of $V_{dd}$ , as shown in the figure, has the following parameters: $V_{dd}$ =3V $\mu_n C_{ox}=100\mu A/V^2$ ; $V_{tn}=0.7 V$ for nMOS $\mu_p C_{ox}=40\mu A/V^2$ ; $|V_{tp}|=0.9 V$ for pMOS The ratio of $\left ( \frac{W}{L} \right )_n$ to $\left ( \frac{W}{L} \right )_p$ is equal to ____(rounded off to 3 decimal places).

In the circuit shown, $V_1=0 \; and \; V_2=V_{dd}$ . The other relevant parameters are mentioned in the figure. Ignoring the effect of channel length modulation and the body effect, the value of $I_{out}$ is _____mA(rounded off to 1 decimal place).

In the circuit shown below, the (W/L) value for $M_{2}$ is twice that for $M_{1}$ . The two nMOS transistors are otherwise identical. The threshold voltage $V_{T}$ for both transistors is 1.0V. Note that $V_{GS} \; for M_{2}$ must be $\gt$ 1.0 V. The voltage (in volts, accurate to two decimal places) at $V_{x}$ is _______.

Two identical nMOS transistors $M_{1}$ and $M_{2}$ are connected as shown below. The circuit is used as an amplifier with the input connected between G and S terminals and the output taken between D and S terminals. $V_{bias}$ and $V_{D}$ are so adjusted that both transistors are in saturation. The transconductance of this combination is defined as $g_{m}=\frac{\partial i_{D}}{\partial V_{GS}}$ while the output resistance is $r_{0}=\frac{\partial V_{GS}}{\partial i_{D}}$ , where $i_{D}$ is the current flowing into the drain of $M_{2}$ . Let $g_{m1}$ , $g_{m2}$ be the transconductances and $r_{01}$ , $r_{02}$ be the output resistances of transistors $M_{1}$ and $M_{2}$ , respectively. Which of the following statements about estimates for $g_{m}$ and $r_{0}$ is correct?

For the circuit shown, assume that the NMOS transistor is in saturation. Its threshold voltage $V _{tn}=1V$ and its transconductance parameter $\mu_{n}C_{OX}(\frac{W}{L})=1mA/V^{2}$ . Neglect channel length modulation and body bias effects. Under these conditions, the drain current $I_{D}$ in mA is ___________.

Assuming that transistors $M_{1}$ and $M_{2}$ are identical and have a threshold voltage of 1V, the state of transistors $M_{1}$ and $M_{2}$ are respectively.

An n-channel enhancement mode MOSFET is biased at $V_{GS}>V_{TH} \; and \; V_{DS}>(V_{GS}-V_{TH})$ , where $V_{GS}$ is the gate-to-source voltage, $V_{DS}$ is the drain-to-source voltage and $V_{TH}$ is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves as a