Sequential Circuit Practice Questions

The circuit consists of a JK flip-flop ($P$) with $J=1, K=1$ (toggling behavior) and a D flip-flop ($Q$) with $D$ connected to the output of $P$.
Initial state: $(P, Q) = (0, 1)$.
Cycle 1: $P$ toggles to $\bar{0} = 1$, and $Q$ captures the previous $P$ value ($0$). State: $(1, 0)$.
Cycle 2: $P$ toggles to $\bar{1} = 0$, and $Q$ captures the previous $P$ value ($1$). State: $(0, 1)$.
Cycle 3: $P$ toggles to $\bar{0} = 1$, and $Q$ captures the previous $P$ value ($0$). State: $(1, 0)$.
Final state after three clock cycles is $P=1, Q=0$.

Synchronous sequential circuits employ a global clock signal to ensure that state transitions occur only when input signals are stable. This architectural constraint inherently mitigates transient logic glitches and race conditions, known as hazards, which pose significant design challenges in asynchronous circuits where transitions are triggered immediately by input changes. While asynchronous circuits are often faster, they lack the predictable timing provided by the clock, making them harder to design and verify for hazard avoidance. Consequently, synchronous circuits prioritize systematic reliability at the cost of additional hardware for clock distribution and critical path propagation delays.

The circuit is a 4-bit Linear Feedback Shift Register (LFSR) where the input to the first flip-flop is determined by the XOR operation of the outputs from the 3rd and 4th flip-flops, represented as $D = Q_3 \oplus Q_4$. With $J = D$ and $K = \overline{D}$ (via the inverter), the circuit performs a standard shift operation combined with this feedback. This configuration generates a maximum-length sequence (m-sequence) with a cycle length of $2^4 - 1 = 15$ bits. Starting from an initial state of $1111$, the sequence of output bits generated is $111100010011010$.

Based on the circuit diagram, the input logic is defined by $D_A = Q_C \oplus Q_D$, while the shift register updates as $D_B = Q_A$, $D_C = Q_B$, and $D_D = Q_C$. Given the state after the third clock pulse is $Q_A Q_B Q_C Q_D = 0001$, we calculate the next state:
$Q_A(\text{next}) = Q_C \oplus Q_D = 0 \oplus 1 = 1$
$Q_B(\text{next}) = Q_A = 0$
$Q_C(\text{next}) = Q_B = 0$
$Q_D(\text{next}) = Q_C = 0$
The resulting state after the fourth clock pulse is $1000$.

A ring counter has n states for n flip-flops. With 5 bits, it cycles through 5 distinct states. Starting from 00001, after 5 pulses it returns to 00001.

Minimum clock period = propagation delay + setup time = 6 + 4 = 10 ns. (Hold time is not directly in the equation for minimum period; it's for avoiding data corruption).

When J=1 and K=1, the JK flip-flop toggles on each clock pulse, acting as a T flip-flop.

For a binary counter, the LSB toggles every clock. So J0=K0=1.

JK flip-flop resolves invalid condition by toggling.

The characteristic equation for JK is Q(next) = JQ' + K'Q. For a T flip-flop, Q(next) = T ⊕ Q. To make them match, substitute T = JQ' + KQ. Then T ⊕ Q = (JQ' + KQ) ⊕ Q = JQ' + K'Q, matching the JK behavior perfectly.

In a synchronous counter, the clock period must be at least T_ff + T_combinational + T_setup. For a 5-bit counter, the longest combinational path is the AND chain for the MSB: 4 AND gates in series? Actually for a binary counter, the enable for each bit is the AND of all lower bits. So for bit 4, the AND has 4 inputs, can be implemented as a tree of 2-input AND gates, giving log2(4)=2 levels? But many counters use ripple carry enable, so delay = (n-1)*T_AND. For n=5, delay = 4 × 5 = 20 ns. Then T_clock >= 10 + 20 + 5 = 35 ns. Frequency = 28.57 MHz. Not matching. Perhaps they assume a single AND gate with multiple inputs with same delay. Then T_clock >= 10+5+5=20 ns -> 50 MHz. So answer 50 MHz.

For a D flip-flop, the next state equals the D input. So D = Qn+1.

A level-triggered latch (e.g., SR latch with enable) is transparent when the clock/enable is high, meaning the output follows the input. Edge-triggered devices change only on edges.

To convert D flip-flop to T flip-flop, we need $Q_{n+1} = T \oplus Q_n$. Since $Q_{n+1} = D$, we set $D = T \oplus Q_n$.

A JK flip-flop in toggle mode (J=K=1) toggles on each clock edge, dividing the frequency by 2. So output frequency = 10/2 = 5 MHz.

For JK flip-flop: transition from 0 to 1 requires J=1 and K can be either 0 or 1 (don't care). So (1, X).

Clock1: FF0: D=Q0'=1, so Q0 becomes 1; FF1: D=Q0(old)=0, so Q1 becomes 0. State = 01. Clock2: FF0: D=Q0'=0, so Q0 becomes 0; FF1: D=Q0(old)=1, so Q1 becomes 1. State = 10. So after 2 clocks, state = 10. Option C. Wait, after 2 clocks: starting 00, after 1:01, after 2:10. So answer C.

Loading time = number of bits × clock period. Clock period = 1/10 MHz = 0.1 μs. So number of bits = 0.8 μs / 0.1 μs = 8.