Q81MediumMCQ

An 8-to-3 priority encoder has outputs A2, A1, A0 and a valid output V. Inputs I7 to I0 with I7 highest priority. The Boolean expression for A2 is:

🚀 Solve in Practice Mode

📖 Explanation

A2 is the most significant bit of the encoded output. It should be 1 for inputs I7, I6, I5, I4. But with priority, if I7=1, then A2=1 regardless of others. If I7=0 and I6=1, then A2=1; if I7=0, I6=0, I5=1 then A2=1; if I7=0,I6=0,I5=0,I4=1 then A2=1. So expression is $I_7 + \overline{I_7}I_6 + \overline{I_7}\overline{I_6}I_5 + \overline{I_7}\overline{I_6}\overline{I_5}I_4$ .

Q82MediumMCQ

The number of select lines required for a 32:1 multiplexer is:

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Q83MediumMCQ

A priority encoder has 4 inputs (I3 I2 I1 I0) and outputs Y1 Y0 and a valid flag V. The priority order is I3 highest, then I2, I1, I0. The output V is 1 if any input is 1. Which of the following expressions is correct for Y1?

🚀 Solve in Practice Mode

📖 Explanation

The highest priority input is I3; if I3=1, Y1=1 regardless of others. If I3=0, then Y1=1 when I2=1. So $Y1 = I_3 + \overline{I_3}I_2$ . This simplifies to $I_3 + I_2$ ? Actually $I_3 + \overline{I_3}I_2 = I_3 + I_2$ (consensus). So both A and B are equivalent. But option B shows the expanded form. However, GATE often expects the minimized form. So answer could be A or B. Usually they give $I_3 + I_2$ . So set correct answer as A. But to avoid confusion, I'll make the options distinct.

Q84MediumMCQ

A 3-to-8 decoder has active high outputs. It is used to implement a Boolean function $F(A,B,C) = \sum m(1,3,5,7)$ . The decoder outputs are connected to a single OR gate. What is the output of the OR gate?

🚀 Solve in Practice Mode

📖 Explanation

The function has minterms 001,011,101,111 - these are all minterms where C=1. So the function simplifies to $C$ . Therefore the OR gate output is $C$ .

Q85MediumMCQ

A 4-bit carry lookahead adder uses generate and propagate functions. If the propagate signals are all 1 and the generate signals are all 0 except for the least significant bit where $G_0=1$ , then the output sum bits will be:

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📖 Explanation

With $P_i=1$ for all i, $G_0=1$ , others 0. Then carry $C_1 = G_0 + P_0C_0 = 1 + 0 =1$ (assuming C0=0). $C_2 = G_1 + P_1C_1 = 0+1*1=1$ , similarly $C_3=1$ , $C_4=1$ . The sum bits $S_i = P_i \oplus C_i$ . So $S_0 = P_0 \oplus C_0 = 1 \oplus 0 =1$ , $S_1 = 1 \oplus C_1 = 1 \oplus 1 =0$ , $S_2 = 1 \oplus 1 =0$ , $S_3 = 1 \oplus 1 =0$ . So the sum is 0001 (LSB first). So answer is 0001.

Q86MediumMCQ

A logic circuit implements the function $F = \overline{A}B\overline{C} + \overline{A}BC + A\overline{B}C + ABC$ . This circuit can be implemented using a single:

🚀 Solve in Practice Mode

📖 Explanation

The expression simplifies to $B\overline{C} + BC = B$ ? Actually $B\overline{C} + BC = B$ . So $F = B$ , independent of A and C. This can be implemented by a 4-to-1 MUX with select lines A and C connecting B to appropriate inputs. Or even simpler. But the minimal MUX would be 2-to-1? With select = B, inputs 0 and 1? Actually $F = B$ can be implemented with a wire. But among options, a 4-to-1 MUX is sufficient. However, the expression is not that; let's recompute: $\overline{A}B\overline{C} + \overline{A}BC = \overline{A}B$ , and $A\overline{B}C + ABC = A C$ . So $F = \overline{A}B + AC$ . That is not a single variable. So the simplification earlier was wrong. Let's test: For A=0,B=1,C=0: term1=1, term2=0, term3=0, term4=0 =>1. For A=0,B=1,C=1: term1=0,term2=1, term3=0, term4=0 =>1. For A=1,B=0,C=1: term1=0,term2=0,term3=1, term4=0 =>1. For A=1,B=1,C=1: term1=0,term2=0,term3=0, term4=1 =>1. For others 0. So truth table: F=1 for (0,1,0),(0,1,1),(1,0,1),(1,1,1). That is $\overline{A}B + AC$ . This can be implemented with a 4-to-1 MUX with select lines A,B. So option B.

Combinational Circuits Practice Questions

📘 Combinational Circuits – Concept Summary