Pipeline Processor Practice Questions

This is a load-use hazard: I2 needs the value of R1, which is only available after the MEM stage of I1. Without forwarding, I2 must stall until I1's WB stage before using R1. The number of stall cycles is typically 2, as I2's ID stage must wait two cycles (EX and MEM of I1). Classic example from GATE 2010 and 2017 on load-use hazards and the need for forwarding.

I1 writes R1, I2 reads R1 → that's a RAW hazard (true dependence). I1 writes R1, I3 reads R1 → also a RAW hazard. I4 uses entirely different registers (R8, R9, R10), so no hazard with I1. This question tests the ability to identify RAW dependencies, which is a fundamental skill in pipelining analysis. Pattern derived from GATE 2007 and 2011 questions.

A structural hazard occurs when two different instructions in the pipeline require the same hardware resource at the same time. Option B describes a classic structural hazard where both instruction fetch and data memory access compete for a single memory port. Option A describes a data hazard, C a control hazard, and D is a function of instruction latency. This question is based on patterns from GATE 2023.[reference:6]

Amdahl's law: New execution time = unaffected time + affected time / speedup. Here unaffected = 20 s, desired new time = 100/5 = 20 s. Then 20 = 20 + 80 / k ⇒ 80/k = 0 ⇒ no finite k can achieve the goal because the serial portion already equals the target time.

If the instruction and data caches are not separate, the pipeline can suffer from a structural hazard: an instruction fetch in the IF stage may conflict with a data memory access in the MEM stage. This requires the pipeline to stall one of the stages, thereby reducing performance. This is a classic example of why Harvard architecture (separate caches) is used in pipelined processors. This question pattern is seen in GATE 2014 and 2022.

RAW (Read After Write) hazards are the most common type of data hazard, occurring when a later instruction reads a register before an earlier instruction writes it (A). WAR (Write After Read) hazards occur when a later instruction writes to a register after an earlier instruction has read it (B). In an in-order pipeline, instructions are issued in order, making WAW hazards unlikely without register renaming (C). Operand forwarding can eliminate many, but not all, RAW hazards (e.g., load-use hazards may require a stall), so D is false.[reference:5]

Interlocking is a hardware mechanism that detects pipeline hazards (data, control, structural) and automatically stalls the pipeline until the hazard is resolved. It ensures correct execution by inserting bubbles (NOPs) where needed. This is a fundamental concept from GATE 2009 and 2018 on pipeline control units.

Register renaming is a technique used in pipelined processors to eliminate false data dependencies, particularly Write-After-Write (WAW) and Read-After-Write (RAW) hazards, by dynamically mapping logical registers to physical registers. This reduces pipeline stalls and improves performance.[reference:1]

I3 updates R1, which the branch condition depends on, so it can't be moved (A). I1 updates R2, used by I3, causing a data hazard if moved (B). I2 updates R4, used by I4 as the memory address, so moving it would change the store location (C). I4 (STORE) uses R1 and R4; executing it in the delay slot is safe whether the branch is taken or not, as memory writes are idempotent in this context (D). This is based on GATE 2009 Q212.[reference:9]

Throughput is the rate at which work (e.g., tasks or instructions) is completed per unit time. This contrasts with latency, which is the time needed for a single operation from start to finish.

I0 finishes WB after 1+1+3+1+1 = 7 cycles. I1 finishes WB after 7 + 6 = 13 cycles. I2 depends on R2 and R5; it waits for I1's result, so it starts at cycle 13+1 = 14, finishes WB at 14+1+1+1+1 = 18? Actually, 1+1+1+1 = 4 more cycles to complete, finishing at 18. I3 depends on R2 and R6; R2 is ready after I2's WB at cycle 18? I2 finishes WB at 18. So I3 starts EX after I2's WB? With forwarding, execution can begin earlier. The correct answer from GATE 2010 is 17 cycles.[reference:3]

I1: IF(1), ID(2), EX(3-5), MEM(6), WB(7) → completes at cycle 7. I2: depends on R1 → forwarding from EX of I1 (cycle 5) allows I2's EX to start at cycle 6 (if no structural conflict). I2's ID stage at cycle 3?? Actually, I2 fetched at cycle 2, ID at cycle 3, stalls until cycle 5? With forwarding, I2 can execute after I1's EX finishes. I2: IF(2), ID(3), stall(4-5), EX(6), MEM(7), WB(8). I3: depends on I1's result availability for STORE. I3: IF(3), ID(4), stall(5?), EX(6? Actually, I3's EX stage may conflict if memory is busy). The typical result from GATE 2016 is 11 cycles.

Superscalar processors have multiple instruction pipelines and can issue and execute multiple instructions in parallel in the same clock cycle (ILP). This is distinct from superpipelining (deep pipelines) or SIMD (vector processors). Based on standard definitions in GATE CS 2006 and 2015 syllabi.

AMAT = Hit time + Miss rate × Miss penalty. Miss rate = 1 - 0.9 = 0.1. AMAT = 1 + 0.1 × 50 = 6 ns.

Non-pipelined time per instruction = 5 cycles/(2.5×10⁹ Hz) = 2 ns. In pipelined processor, the weighted CPI = 1 + 0.3×0.05×50 + 0.1×0.5×2 = 1 + 0.75 + 0.1 = 1.85. Pipelined clock period = 1/(2×10⁹) = 0.5 ns, so average execution time per instruction = 1.85×0.5 = 0.925 ns. Hence speedup = 2/0.925 = 2.16.

Amdahl's law states the maximum speedup is limited by the sequential portion of the program. As the number of cores increases, this sequential portion becomes the dominant factor, limiting performance gains regardless of the number of parallel cores.

DVFS reduces clock frequency and voltage to save energy during low-demand periods. Performance scales less than quadratically with frequency, so moderate frequency reductions yield large power savings. It does not eliminate caches or let all cores run at maximum frequency simultaneously without thermal/power limits.

If branch resolution occurs in the EX stage, instructions in IF, ID, and possibly EX (if the condition is computed at the end) stages are invalid. Typically, the instruction in the EX stage (the branch itself) is not considered flushed, but the next instruction (in ID) and the next instruction after that (in IF) are flushed. Actually, the branch instruction itself is in the EX stage, and the following two instructions (ID and IF) must be flushed. This constitutes 2 instructions being flushed. However, in some designs, the instruction directly following the branch (in the delay slot) might be conditionally executed. Common GATE answers indicate 2 instructions flushed if the pipeline has a 5-stage design. This question is based on GATE 2012's discussion on branch penalties.