Machine Instruction Practice Questions

For an I-type instruction like ADDI, only the ALU, Register File (to read register R2), and Sign Extender (to extend the immediate value) are active. Data Memory is not accessed, as the result is written back to a register, not to memory.

Stack machines use a stack for operands (A). Accumulator machines have one implicit accumulator operand (B). For the same computation, stack machines often require more instructions (push/pop) (C). Accumulator machines may have very compact instructions, but not necessarily smaller than stack instructions. Statement D is not always true. Therefore, A, B, C are correct.

The correct sequence is: (1) Complete the current instruction. (2) Save the PC (and other context). (3) Load the starting address of the ISR. (4) Execute the ISR. (5) Restore the PC to resume the interrupted program. Option A follows this correct sequence.

Register indirect: EA = contents of register (B). Indexed: EA = base register + index register (D). Base with displacement: EA = base register + constant (A). Relative: EA = PC + constant (C). So mapping 1-B, 2-D, 3-A, 4-C is correct.

Relative addressing uses the Program Counter as the base and adds a displacement (offset) to compute the effective address. It is commonly used for branch instructions. Option A is correct.

The Instruction Set Architecture (ISA) serves as the interface between hardware and software. It defines the set of instructions that a processor can execute, the registers, memory addressing modes, etc. Software (compiler, assembler) works at the ISA level, while hardware implements it. So ISA is the boundary.

A typical instruction pipeline includes stages such as IF (fetch), ID (decode), EX (execute), MEM (memory access), and WB (write back). Context switch is an operating system function and not part of the instruction pipeline hardware.

CISC architectures typically have a limited number of general-purpose registers due to the complexity of the instruction set and the use of memory operands directly. RISC architectures emphasize a large number of registers to reduce memory accesses. So, 'Large number of general-purpose registers' is not a characteristic of CISC; it is characteristic of RISC.

In a daisy chain priority scheme, the interrupt priority is determined by physical proximity to the CPU. The device closest to the CPU (D1) has the highest priority because it will receive the interrupt acknowledgment first and can block the propagation of the signal to downstream devices.

The first machine cycle for any instruction is the fetch cycle, during which the CPU fetches the instruction from memory into the Instruction Register (IR). This is true for all instructions, regardless of their operation. The fetch cycle always precedes the execute cycle or any other cycles.

In base-register addressing (also called base-offset or displacement addressing), the effective address is the sum of a base register's content and a constant displacement provided in the instruction. Indexed addressing uses index register plus base, but base-register specifically refers to adding a constant. The question describes base-register addressing.